1. Field of the Invention
The embodiments discussed herein relate to a semiconductor device.
2. Description of the Related Art
Known as a start-up element of a start-up circuit used in a conventional switching power supply device, one high voltage junction field effect transistor (JFET) has plural source regions disposed in a planar layout on a circular perimeter along the circumference of an input pad having a circular planar shape (see, e.g., Japanese Laid-Open Patent Publication No. 2008-153636). In Japanese Laid-Open Patent Publication No. 2008-153636, a resistive element connected in parallel to the start-up element is disposed between the input pad and a gate electrode wire of the high voltage JFET. The resistive element includes a thin film resistor including polysilicon (poly-Si) or the like disposed to form a spiral planar shape on an edge termination structure of the start-up element.
The structure of the JFET forming the conventional start-up element will be described with reference to FIGS. 14 to 16. FIG. 14 is a plan diagram of a planar layout of the conventional semiconductor device. FIG. 15 is a cross-sectional view taken along a cutting line AA-AA′ in FIG. 14. FIG. 16 is an enlarged plan diagram of a portion of FIG. 14. In FIGS. 14 and 16, metal wires are indicated by dotted lines. FIG. 16 depicts a planar layout of a portion near an outer peripheral end of the resistive element including the thin film resistor 120 including polysilicon (hereinafter, referred to as “polysilicon resistor”). In a conventional JFET 100 depicted in FIGS. 14 to 16, a p-type gate region 102 is selectively disposed in the surface layer of the front surface of a p-type semiconductor substrate 101. Reference numeral “106” denotes a p+-type contact region inside the p-type gate region 102.
An n-type drift layer 103 is selectively disposed so as to have a predetermined width and enter into a portion of the p-type gate region 102, in the surface layer of the front surface of the p-type semiconductor substrate 101. An n+-type source region 104 is selectively disposed in the surface layer of the front surface of the p-type semiconductor substrate 101, at the point into which the n-type drift region 103 enters. An n+-type drain region 105 that faces the n+-type source region 104 sandwiching the n-type drift region 103 therebetween is selectively disposed in the surface layer of the front surface of the p-type semiconductor substrate 101, at a point away from the n+-type source region 104. The n+-type source region 104 is disposed on the circumference at equal intervals from the n+-type drain region 105.
A gate polysilicon electrode 107 is disposed to extend over the p-type gate region 102 and the n-type drift region 103, at the position not depicted at which the n-type drift region 103 contacts the p-type gate region 102. At the position at which the n+-type source region 104 is disposed, the gate polysilicon electrode 107 is disposed on a local oxidation of silicon (LOCOS) oxide film 108 on the n-type drift region 103. An interlayer insulating film 109 is disposed on the regions that are the LOCOS oxide film 108, the gate polysilicon electrode 107, and the surface layer of the front surface of the p-type semiconductor substrate 101.
In the interlayer insulating film 109, a polysilicon resistor 120 is disposed in a portion that faces the n-type drift region 103 in the depth direction, sandwiching the LOCOS oxide film 108 therebetween. The polysilicon resistor 120 has a planar shape forming a spiral extending from the inner side (the side of the n+-type drain region 105) toward the outer side (the side of the n+-type source region 104). The polysilicon resistor 120, at the outer peripheral end thereof, is electrically connected to a ground terminal wire 121 through a ground (ground) contact portion 123 that penetrates the interlayer insulating film 109. The polysilicon resistor 120 is connected to a voltage division terminal wire 122 through a voltage division point contact portion 124 closer to the inner peripheral end side than the ground contact portion 123 in an outermost circumference 120b. 
A gate electrode wire 110, a drain electrode wire 111, and a source electrode wire 112 are disposed on the interlayer insulating film 109. The gate electrode wire 110 is disposed to surround the n+-type drain region 105, the n-type drift region 103, and the n+-type source region 104, and faces the p-type gate region 102 in the depth direction, sandwiching the interlayer insulating film 109 therebetween. The gate electrode wire 110 is electrically connected to the p-type gate region 102 and the gate polysilicon electrode 107 through a gate contact portion 113 that penetrates the interlayer insulating film 109. The gate electrode wire 110 is normally grounded.
The drain electrode wire 111 faces the n+-type drain region 105 in the depth direction, sandwiching the interlayer insulating film 109 therebetween. The drain electrode wire 111 is electrically connected to the n+-type drain region 105 through a drain contact portion 114 that penetrates the interlayer insulating film 109. The drain electrode wire 111 extends outward on the interlayer insulating film 109, and faces an innermost circumference 120a of the polysilicon resistor 120 in the depth direction, sandwiching the interlayer insulating film 109 therebetween. The drain electrode wire 111 is electrically connected to the polysilicon resistor 120 through a resistive element contact portion 116 that penetrates the interlayer insulating film 109.
The source electrode wire 112 is disposed to surround the n+-type drain region 105 and the n-type drift region 103, and faces the n+-type source region 104 in the depth direction, sandwiching the interlayer insulating film 109. The source electrode wire 112 is electrically connected to the n+-type source region 104 through a source contact portion 115 that penetrates the interlayer insulating film 109. The source electrode wire 112 extends inward on the interlayer insulating film 109, and faces the outermost circumference 120b of the polysilicon resistor 120 and the gate polysilicon electrode 107 in the depth direction, sandwiching the interlayer insulating film 109 therebetween.